This invention relates to a semiconductor memory such as a static random access memory (RAM) comprising a flip-flop circuit as a memory cell and to a method of producing the semiconductor memory.
Recently, it is a matter of serious concern in this field to improve the access time of a semiconductor memory. A static RAM comprising MOS transistors of polycrystalline silicon (polysilicon) gate type, is disclosed in, for example, U.S. Pat. No. 4,110,776 issued to G. R. Mohan Rao et al. It is desirable to improve the access time of the static RAM of polysilicon gate type. For improving the access time of the static RAM, the gate oxide film of each of the MOS transistors included in the RAM is formed thin in general so as to increase the conductance gm thereof. Thus, it is desirable to make the gate oxide film thin with respect to the MOS transistors included in the peripheral circuits of the memory matrix, such as the input buffer circuit, decoder circuit, sense amplifier, or output buffer circuit. Since the MOS transistor for selecting the memory cell is also formed together with the MOS transistor included in the peripheral circuit, the gate oxide film of the MOS transistor for selecting the memory cell is also made thin.
In order to obtain an access time of, for example, 50 n sec or less, it is particularly important to solve the problem of delay time encountered by the row decoder, which serves to select the row of memory cells, when the address line is changed from a low level to a high level. However, the conventional address line is formed of polysilicon. In addition, the gate oxide film is formed thin in each of the MOS transistors for selecting the memory cells as described above, leading to a relatively large capacitance. It follows that a large RC time constant causes delay in the rise of the signal generated from the row decoder when selecting the address line.